EEL Module 3: Electronics & Semiconductors

Electrical Engineer License Certification Program

25% Complete

1. Semiconductor Physics Fundamentals

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Introduction to Semiconductors

Semiconductors form the foundation of modern electronic devices. Understanding their physics is essential for designing and analyzing electronic circuits.

Semiconductor Structure and Band Diagram

Figure 1: Semiconductor crystal structure showing energy bands and electron movement

Semiconductor Material Properties Calculator

Key Semiconductor Properties:

  • Electrical conductivity between conductors and insulators
  • Temperature-dependent conductivity
  • Ability to control conductivity through doping
  • Rectifying behavior at junctions
  • Photoelectric and thermoelectric effects

Energy Band Structure

Conduction Band

Free electrons carry current

Band Gap (Eg)

Forbidden energy states

Valence Band

Bound electrons

Intrinsic Semiconductors

Pure semiconductor crystals at absolute zero have completely filled valence bands and empty conduction bands.

Intrinsic Silicon
Band Gap: 1.12 eV
Conductivity: Very low at room temp
Electron-Hole Pairs: 1.5×10¹⁰/cm³
Intrinsic Germanium
Band Gap: 0.66 eV
Conductivity: Higher than Silicon
Electron-Hole Pairs: 2.4×10¹³/cm³
Intrinsic Gallium Arsenide
Band Gap: 1.42 eV
Conductivity: High electron mobility
Applications: High-speed devices

Doped Semiconductors

Controlled impurities (dopants) are added to semiconductors to modify their electrical properties.

N-Type Semiconductors

Donor impurities (Group V elements like Phosphorus, Arsenic) add extra electrons:

N-Type Doping
Dopant: P, As, Sb
Majority Carriers: Electrons
Minority Carriers: Holes
Conductivity: High

P-Type Semiconductors

Acceptor impurities (Group III elements like Boron, Gallium) create "holes":

P-Type Doping
Dopant: B, Al, Ga
Majority Carriers: Holes
Minority Carriers: Electrons
Conductivity: High

Carrier Concentration

For intrinsic semiconductors:

n × p = n_i²

Where n = electron concentration, p = hole concentration, n_i = intrinsic carrier concentration

For doped semiconductors:

N-type: n ≈ N_D, p ≈ n_i²/N_D
P-type: p ≈ N_A, n ≈ n_i²/N_A

Where N_D = donor concentration, N_A = acceptor concentration

Carrier Concentration Example

Given: Silicon doped with 10¹⁶ cm⁻³ phosphorus atoms at 300K
n_i = 1.5×10¹⁰ cm⁻³
Solution:
n ≈ N_D = 10¹⁶ cm⁻³ (electrons)
p = n_i²/N_D = (1.5×10¹⁰)²/10¹⁶ = 2.25×10⁴ cm⁻³ (holes)

Charge Carrier Transport

Electric current in semiconductors results from the movement of charge carriers.

Drift Current

Current due to electric field acceleration:

J_n = q × n × μ_n × E (electrons)
J_p = q × p × μ_p × E (holes)

Where μ_n, μ_p are electron and hole mobilities

Diffusion Current

Current due to carrier concentration gradients:

J_n(diff) = q × D_n × dn/dx
J_p(diff) = -q × D_p × dp/dx

Where D_n, D_p are diffusion coefficients

Mobility Values (300K)

Silicon:
μ_n = 1350 cm²/(V·s)
μ_p = 480 cm²/(V·s)
Germanium:
μ_n = 3900 cm²/(V·s)
μ_p = 1900 cm²/(V·s)
GaAs:
μ_n = 8500 cm²/(V·s)
μ_p = 400 cm²/(V·s)

2. PN Junction Diodes

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PN Junction Formation

When p-type and n-type semiconductors are joined, a PN junction forms with unique electrical properties.

PN Junction Diode Structure and Characteristics

Figure 2: PN junction diode structure showing depletion region and characteristic curve

PN Junction Diode Analysis Calculator

Junction Formation Process

  1. Initial Contact: Free carriers diffuse across the junction
  2. Depletion Region: Fixed ions create electric field
  3. Equilibrium: Diffusion current equals drift current
  4. Built-in Potential: Contact potential develops across junction

Built-in Potential

The contact potential that exists across a PN junction at equilibrium:

V_bi = (kT/q) × ln(N_A × N_D / n_i²)

Where k = Boltzmann constant, T = temperature, q = electron charge

Built-in Potential Calculation

Given:
N_A = 10¹⁶ cm⁻³ (p-type)
N_D = 10¹⁵ cm⁻³ (n-type)
n_i = 1.5×10¹⁰ cm⁻³ (silicon)
T = 300K
Solution:
V_bi = (25.85 mV) × ln(10¹⁶ × 10¹⁵ / (1.5×10¹⁰)²)
V_bi = 0.02585 × ln(10³¹ / 2.25×10²⁰)
V_bi = 0.02585 × ln(4.44×10¹⁰) = 0.65V

Diode Current-Voltage Relationship

The Shockley diode equation describes current flow through a PN junction:

I = I_s × (e^(V/(n×V_T)) - 1)

Where:

  • I_s = Reverse saturation current
  • V = Applied voltage
  • n = Ideality factor (1-2)
  • V_T = Thermal voltage = kT/q ≈ 25.85 mV at 300K

Diode Regions of Operation

Forward Bias

Voltage: V > 0
Current: Exponential increase
Barrier: Reduced
Turn-on Voltage: ~0.6-0.7V (Si)

Reverse Bias

Voltage: V < 0
Current: Reverse saturation
Barrier: Increased
Breakdown: High reverse voltage

Zero Bias

Voltage: V = 0
Current: I = 0
State: Equilibrium
Depletion: Maximum width

Reverse Saturation Current

The small current that flows in reverse bias due to minority carriers:

I_s = q × A × (D_p × p_n₀/L_p + D_n × n_p₀/L_n)

Where A = junction area, L = diffusion length

Diode Current Calculation

Given:
I_s = 10⁻¹² A, n = 1, V_f = 0.7V, T = 300K
Forward current:
I = 10⁻¹² × (e^(0.7/0.02585) - 1)
I = 10⁻¹² × (e^27.08 - 1) ≈ 10⁻¹² × 6.2×10¹¹ = 0.62A
Reverse current:
I = 10⁻¹² × (e^(-0.7/0.02585) - 1)
I ≈ -10⁻¹² A (reverse saturation current)

Junction Capacitance

PN junctions exhibit capacitance due to the depletion region acting as a dielectric.

Junction Capacitance

C_j = ε_s × A / W

Where W = depletion width, ε_s = semiconductor permittivity

Depletion Width

W = √[(2×ε_s×V_bi)/(q) × (1/N_A + 1/N_D)]

Junction Capacitance Example

Given:
A = 10⁻⁶ m², N_A = 10¹⁶ cm⁻³, N_D = 10¹⁵ cm⁻³
ε_s = 11.7 × ε₀ = 11.7 × 8.85×10⁻¹² F/m
V_bi = 0.65V
Solution:
W = √[(2 × 11.7×8.85×10⁻¹² × 0.65)/(1.6×10⁻¹⁹) × (10⁻⁶ + 10⁻⁷)]
W ≈ 1.2×10⁻⁶ m = 1.2 μm
C_j = 11.7×8.85×10⁻¹² × 10⁻⁶ / 1.2×10⁻⁶ = 86 pF

Breakdown Mechanisms

Two primary breakdown mechanisms occur in reverse-biased PN junctions:

Zener Breakdown

Voltage: < 5V
Mechanism: Quantum tunneling
Temperature: Negative coefficient
Device: Zener diode

Avalanche Breakdown

Voltage: > 5V
Mechanism: Impact ionization
Temperature: Positive coefficient
Device: Avalanche diode

Diode Models

Different levels of circuit models are used depending on application requirements:

Diode Circuit Models

Ideal Diode Model

Forward: Short circuit
Reverse: Open circuit
Use: High-level analysis

Constant Voltage Drop

Forward: 0.7V drop
Reverse: Open circuit
Use: Approximate analysis

Exponential Model

Forward: I = I_s(e^V/nVt - 1)
Reverse: I = -I_s
Use: Precise analysis

3. Bipolar Junction Transistors (BJTs)

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BJT Fundamentals

Bipolar Junction Transistors are three-terminal devices that can amplify signals or act as electronic switches.

Bipolar Junction Transistor Structure and Characteristics

Figure 3: BJT transistor structure showing NPN configuration and characteristic curves

BJT Transistor Biasing Calculator

BJT Characteristics:

  • Three-terminal device: Base, Collector, Emitter
  • Current-controlled current source
  • Two PN junctions (base-emitter and base-collector)
  • Current gain characteristics (β or h_FE)
  • Three operating regions: active, saturation, cutoff

BJT Structures

NPN Transistor

Structure: N-P-N
Common Use: Signal amplification
Current Flow: Electrons majority
Applications: Most common type

PNP Transistor

Structure: P-N-P
Common Use: Complementary circuits
Current Flow: Holes majority
Applications: Push-pull stages

BJT Current Relations

Fundamental current relationships in bipolar transistors:

Emitter Current: I_E = I_B + I_C

Collector Current: I_C = β × I_B

Base Current: I_B = I_E / (β + 1)

Current Gain: β = I_C / I_B = α/(1 - α)

Where α = I_C/I_E is the common-base current gain

BJT Current Analysis

Given: β = 100, I_B = 50 μA
Solution:
I_C = β × I_B = 100 × 50×10⁻⁶ = 5 mA
I_E = I_B + I_C = 50×10⁻⁶ + 5×10⁻³ = 5.05 mA
α = I_C/I_E = 5/5.05 = 0.99

BJT Operating Regions

BJTs can operate in different regions depending on bias conditions:

Active Region (Forward Active)

BE Junction: Forward biased
BC Junction: Reverse biased
Use: Amplification
Current: I_C = βI_B

Saturation Region

BE Junction: Forward biased
BC Junction: Forward biased
Use: Switching (ON)
V_CE(sat): ~0.2V

Cutoff Region

BE Junction: Reverse biased
BC Junction: Reverse biased
Use: Switching (OFF)
Currents: Very small

Early Effect

The variation of collector current with collector-emitter voltage due to base-width modulation:

I_C = I_S × e^(V_BE/V_T) × (1 + V_CE/V_A)

Where V_A is the Early voltage (typically 50-100V)

Early Effect Example

Given: V_A = 100V, V_CE changes from 5V to 15V
Solution:
At V_CE = 5V: I_C = I_S × (1 + 5/100) = 1.05 × I_S
At V_CE = 15V: I_C = I_S × (1 + 15/100) = 1.15 × I_S
Current increase = (1.15 - 1.05)/1.05 = 9.5%

BJT Configurations

Three basic amplifier configurations based on the common terminal:

Common Emitter (CE)

  • Input: Base
  • Output: Collector
  • Common: Emitter
  • Voltage gain: High
  • Current gain: β
  • Phase shift: 180°

Common Collector (CC)

  • Input: Base
  • Output: Emitter
  • Common: Collector
  • Voltage gain: ~1
  • Current gain: β+1
  • Phase shift: 0°

Common Base (CB)

  • Input: Emitter
  • Output: Collector
  • Common: Base
  • Voltage gain: High
  • Current gain: α ≈ 1
  • Phase shift: 0°

Biasing Circuits

Proper biasing is essential for linear operation of BJT amplifiers.

Common Biasing Techniques

Fixed Bias

Simplicity: Very simple
Stability: Poor
β Sensitivity: High
Use: Basic circuits

Voltage Divider Bias

Simplicity: Moderate
Stability: Good
β Sensitivity: Low
Use: Most amplifiers

Emitter Bias

Simplicity: Moderate
Stability: Excellent
Temperature: Compensated
Use: High stability

Voltage Divider Bias Design

Given: V_CC = 12V, I_C = 1mA, V_CE = 6V, β = 100
Step 1 - Emitter resistor:
V_E = I_C × R_E = 0.2 × V_CC = 2.4V (typical)
R_E = 2.4V / 1mA = 2.4kΩ
Step 2 - Collector resistor:
V_RC = V_CC - V_CE - V_E = 12 - 6 - 2.4 = 3.6V
R_C = 3.6V / 1mA = 3.6kΩ
Step 3 - Base voltage:
V_B = V_BE + V_E = 0.7 + 2.4 = 3.1V
Step 4 - Base resistors:
Choose R2 to draw 10× I_B (stiff divider)
I_B = I_C/β = 1mA/100 = 10μA
I_R2 ≈ 100μA, so R2 = 3.1V/100μA = 31kΩ
R1 = (12V - 3.1V)/100μA = 89kΩ

BJT High-Frequency Effects

At high frequencies, BJT performance is limited by parasitic capacitances and transit time effects.

Transit Time Effects

  • Base Transit Time: Time for carriers to cross base region
  • Collector Storage Time: Time to remove stored charge in saturation
  • Cutoff Frequency: f_T where current gain = 1
f_T = 1/(2π × τ)

Where τ is the total transit time

Small-Signal Parameters

Transconductance: g_m = I_C/V_T
Input resistance: r_π = β/g_m
Output resistance: r_o = V_A/I_C
Base resistance: r_b ≈ 100-300Ω

4. Field Effect Transistors (FETs)

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FET Fundamentals

Field Effect Transistors are voltage-controlled devices that use electric fields to control current flow.

FET Structure and Transfer Characteristics

Figure 4: MOSFET structure showing channel formation and transfer characteristics

FET Transistor Analysis Calculator

FET Characteristics:

  • Voltage-controlled current source
  • High input impedance (megohms to gigaohms)
  • Low power consumption
  • Unipolar operation (only one carrier type)
  • Four terminals: Gate, Source, Drain, Body

Junction FET (JFET)

JFETs use reverse-biased PN junctions to control channel conductivity.

JFET Operation

N-Channel JFET

Channel: N-type semiconductor
Gate: P-type regions
Gate Control: Reverse bias
Current: Electrons

P-Channel JFET

Channel: P-type semiconductor
Gate: N-type regions
Gate Control: Reverse bias
Current: Holes

JFET Characteristics

Key parameters and characteristics of JFETs:

Pinch-off Voltage (V_P)

Definition: V_GS where channel closes
Typical Value: -2V to -8V
N-Channel: Negative
P-Channel: Positive

Drain-Source Saturation Current (I_DSS)

Definition: Max ID at V_GS = 0
Range: 1mA to 100mA
Significance: Device size indicator
Temperature: Negative TC

JFET Current-Voltage Relationship

The drain current in the saturation region:

I_D = I_DSS × (1 - V_GS/V_P)²

For V_GS between 0 and V_P (pinch-off voltage)

JFET Current Calculation

Given: I_DSS = 20mA, V_P = -4V, V_GS = -2V
Solution:
I_D = 20mA × (1 - (-2)/(-4))²
I_D = 20mA × (1 - 0.5)² = 20mA × 0.25 = 5mA

MOSFET Fundamentals

Metal-Oxide-Semiconductor FETs use an insulated gate electrode for superior control.

MOSFET Types

Enhancement NMOS

Channel: N-type (induced)
Threshold (V_TH): +1-3V
Normally: OFF (no channel)
Control: Positive V_GS

Enhancement PMOS

Channel: P-type (induced)
Threshold (V_TH): -1 to -3V
Normally: OFF (no channel)
Control: Negative V_GS

Depletion NMOS

Channel: N-type (built-in)
Threshold (V_TH): -2 to -4V
Normally: ON (channel present)
Control: V_GS can enhance/deplete

MOSFET Characteristics

Key MOSFET parameters and equations:

Enhancement MOSFET in Saturation

I_D = (μ_n × C_ox × W/L) × (V_GS - V_TH)² / 2

Where:

  • μ_n = electron mobility
  • C_ox = oxide capacitance per unit area
  • W/L = width-to-length ratio
  • V_TH = threshold voltage

Transconductance

g_m = √(2 × μ_n × C_ox × W/L × I_D)

MOSFET Design Example

Given: V_TH = 2V, μ_n × C_ox = 50μA/V², W/L = 10, V_GS = 5V
Solution:
I_D = (50×10⁻⁶ × 10) × (5-2)² / 2
I_D = 500×10⁻⁶ × 9 / 2 = 2.25mA
Transconductance:
g_m = √(2 × 50×10⁻⁶ × 10 × 2.25×10⁻³)
g_m = √(2.25×10⁻³) = 47.4μS

Power MOSFETs

High-power MOSFETs designed for switching applications in power electronics.

Power MOSFET Characteristics

Vertical DMOS

Structure: Vertical current flow
Voltage Range: 20V - 1000V
Current Range: 1A - 100A
RDS(on): 1mΩ - 100mΩ

Lateral DMOS

Structure: Lateral current flow
Voltage Range: 12V - 200V
Current Range: 1A - 50A
Applications: IC design

FET Biasing

FET biasing is generally simpler than BJT biasing due to the absence of gate current.

FET Biasing Techniques

Self-Bias

Components: R_S only
Advantages: Simple, stable
Applications: Small-signal amplifiers
V_GS: -I_D × R_S

Voltage Divider Bias

Components: R1, R2, R_S
Advantages: Precise control
Applications: Linear amplifiers
V_GS: V_G - I_D × R_S

FET vs BJT Comparison

Key differences between FETs and BJTs:

Input Characteristics

FET: Very high (MΩ-GΩ)
BJT: Low (kΩ)
FET: No input current
BJT: Base current required

Gain Characteristics

FET: Voltage controlled
BJT: Current controlled
FET: Transconductance g_m
BJT: Current gain β

Switching Speed

FET: Very fast (low capacitance)
BJT: Moderate (storage time)
FET: No minority carrier storage
BJT: Charge storage effects

5. Operational Amplifiers

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Op-Amp Fundamentals

Operational amplifiers are high-gain differential voltage amplifiers with very high input impedance and low output impedance.

Operational Amplifier Internal Structure and Symbol

Figure 5: Operational amplifier internal structure and circuit symbol

Operational Amplifier Circuit Calculator

Ideal Op-Amp Characteristics:

  • Infinite open-loop gain (A_OL → ∞)
  • Infinite input impedance (Z_in → ∞)
  • Zero output impedance (Z_out → 0)
  • Infinite bandwidth (BW → ∞)
  • Zero offset voltage (V_os → 0)
  • Infinite CMRR and PSRR

Basic Op-Amp Symbol

Non-Inverting Input (+)
+
V+
Inverting Input (-)
-
V-
▶
Output
V_out
Supply Rails: VCC+ = +15V, VCC- = -15V (typical)

Golden Rules of Op-Amps

For ideal op-amps in negative feedback:

  1. No Current Rule: Input currents are zero (I+ = I- = 0)
  2. Virtual Short Rule: V+ = V- (when output is within linear range)

Basic Op-Amp Configurations

Inverting Amplifier

A_v = -R_f / R_i

Output is 180° out of phase with input

Inverting Amplifier Design

Given: R_i = 10kΩ, Desired gain = -10
Solution:
A_v = -R_f/R_i = -10
R_f = 10 × R_i = 100kΩ
Check:
If V_in = 1V, then V_out = -10V
I_in = V_in/R_i = 1V/10kΩ = 100μA
I_f = I_in = 100μA (virtual ground)
V_out = -I_f × R_f = -100μA × 100kΩ = -10V ✓

Non-Inverting Amplifier

A_v = 1 + (R_f / R_i)

Output is in phase with input

Non-Inverting Amplifier Design

Given: R_i = 10kΩ, Desired gain = 11
Solution:
A_v = 1 + R_f/R_i = 11
R_f/R_i = 10, so R_f = 100kΩ
Voltage follower (unity gain):
R_f = 0, R_i = ∞ (wire)
A_v = 1, V_out = V_in

Summing Amplifier

V_out = -(R_f/R_1 × V_1 + R_f/R_2 × V_2 + R_f/R_3 × V_3 + ...)

Difference Amplifier

V_out = (R_f/R_i) × (V_2 - V_1)

When R_1 = R_2 and R_f = R_g

Op-Amp Specifications

Real op-amp parameters that deviate from ideal behavior:

DC Specifications

Open-loop Gain: 80-140 dB
Input Offset Voltage: 0.1-10 mV
Input Bias Current: nA-μA
CMRR: 60-120 dB

AC Specifications

Unity Gain BW: 1-100 MHz
Slew Rate: 0.5-100 V/μs
Settling Time: 0.1-10 μs
Noise: nV/√Hz

Output Specifications

Output Impedance: 10-100 Ω
Output Swing: ±10-14V (from rails)
Short Circuit Current: 5-50 mA
Load Drive: 2kΩ minimum

Frequency Response

Op-amps have limited bandwidth due to internal compensation:

f_CL = GBW / A_CL

Where GBW is gain-bandwidth product, A_CL is closed-loop gain

Frequency Response Example

Given: GBW = 1 MHz, Closed-loop gain = 100
Solution:
f_CL = 1 MHz / 100 = 10 kHz
At gain = 1: f_CL = 1 MHz
At gain = 10: f_CL = 100 kHz
At gain = 100: f_CL = 10 kHz

Slew Rate

Maximum rate of change of output voltage:

SR = dV_out/dt (max)

Determines maximum frequency for large signals:

f_max = SR / (2π × V_peak)

Slew Rate Limitation

Given: SR = 0.5 V/μs, V_peak = 5V
Maximum frequency:
f_max = 0.5×10⁶ / (2π × 5) = 15.9 kHz
Interpretation:
Above 15.9 kHz, the output cannot follow the input
Slew rate limiting occurs first

Op-Amp Applications

Active Filters

Low-Pass Filter

fc = 1/(2πRC)

Attenuates high frequencies

Applications: Anti-aliasing, noise reduction

High-Pass Filter

fc = 1/(2πRC)

Attenuates low frequencies

Applications: AC coupling, DC blocking

Band-Pass Filter

fc_low = 1/(2πR1C1)

fc_high = 1/(2πR2C2)

Applications: Tuned circuits, selectivity

Notch Filter

Rejects specific frequency

Applications: 60 Hz hum removal

Comparator

Op-amp without feedback used as voltage comparator:

Output States:
If V+ > V-: V_out = +V_sat
If V+ < V-: V_out = -V_sat

Integrator

V_out = -(1/RC) × ∫V_in dt

Output voltage is integral of input voltage

Differentiator

V_out = -RC × dV_in/dt

Output voltage is derivative of input voltage

Assessment Quiz

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Test Your Knowledge

Answer the following questions to assess your understanding of electronics and semiconductors.

Question 1: Semiconductor Band Gap

What is the band gap energy of intrinsic silicon at room temperature?

  • A) 0.66 eV
  • B) 1.12 eV
  • C) 1.42 eV
  • D) 2.1 eV

Question 2: PN Junction

In a forward-biased PN junction diode, the current is approximately:

  • A) Proportional to voltage
  • B) Exponentially related to voltage
  • C) Inversely proportional to voltage
  • D) Independent of voltage

Question 3: BJT Current Gain

In a BJT with β = 80 and base current of 25μA, what is the collector current?

  • A) 1.6 mA
  • B) 2.0 mA
  • C) 2.5 mA
  • D) 3.2 mA

Question 4: MOSFET Threshold Voltage

An enhancement NMOS transistor has V_TH = 2V. For conduction, V_GS must be:

  • A) > 2V
  • B) < -2V
  • C) > 0V
  • D) Any value

Question 5: Op-Amp Golden Rules

According to the virtual short rule for op-amps:

  • A) V+ - V- = V_out
  • B) V+ = V-
  • C) V+ + V- = 0
  • D) V+ × V- = V_out

Question 6: Inverting Amplifier

An inverting amplifier has R_i = 5kΩ and R_f = 50kΩ. What is the voltage gain?

  • A) -5
  • B) -10
  • C) 10
  • D) 55

Question 7: JFET Pinch-off

The pinch-off voltage of an N-channel JFET is -4V. The transistor will be pinched off when:

  • A) V_GS > -4V
  • B) V_GS < -4V
  • C) V_GS = -4V
  • D) V_GS = 0V

Question 8: FET vs BJT

The main advantage of FETs over BJTs is:

  • A) Higher gain
  • B) Higher input impedance
  • C) Lower cost
  • D) Higher frequency response

Question 9: Op-Amp Slew Rate

An op-amp has slew rate of 1 V/μs. The maximum frequency for a 5V peak sinusoidal output is:

  • A) 15.9 kHz
  • B) 31.8 kHz
  • C) 63.7 kHz
  • D) 127 kHz

Question 10: Power Dissipation

A transistor operates with V_CE = 5V and I_C = 100mA. The power dissipation is:

  • A) 0.5 W
  • B) 1.0 W
  • C) 5.0 W
  • D) 10.0 W

Quiz Results

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